An IGFET is a semiconductor device in which a gate dielectric layer electrically insulates a gate electrode from a channel zone extending between a source zone and a drain zone. The channel zone in an enhancement-mode IGFET is part of a body region, often termed the substrate or substrate region, which forms respective pn junctions with the source and drain. In an enhancement-mode IGFET, the channel zone consists of all the semiconductor material between the source and drain. During IGFET operation, charge carriers move from the source to the drain through a channel induced in the channel zone along the upper semiconductor surface. The threshold voltage is the value of the gate-to-source voltage at which the IGFET starts to conduct current for a given definition of the threshold (minimum) conduction current.
A depletion region extends along the junction between the source and the body region. Another depletion region extends along the junction between the drain and the body region. A high electric field is present in each depletion region. Under certain conditions, especially when the channel length is small, the drain depletion region can laterally extend to the source depletion region and merge with it along or below the upper semiconductor surface. The merging of the source and drain depletion regions along the upper semiconductor surface is termed surface punchthrough. The merging of the two depletion regions below the upper semiconductor surface is termed bulk punchthrough. When surface or bulk punchthrough occurs, the operation of the IGFET cannot be controlled with its gate electrode. Both types of punchthrough need to be avoided.
Various techniques have been employed to improve the performance of IGFETs, including those operating in the short-channel regime, as IGFET dimensions have decreased. One performance improvement technique involves providing an IGFET with a two-part drain for reducing the electric field at the drain so as to avoid hot carrier injection into the gate dielectric layer. The IGFET is also commonly provided with a similarly configured two-part source. Another conventional performance improvement technique is to increase the dopant concentration of the channel zone in a pocket portion along the source for inhibiting surface punchthrough as channel length is reduced and for shifting generally undesired roll-off of the threshold voltage to shorter channel length. Similar to how the IGFET is provided with a two-part source analogous to the two-part drain, the dopant concentration is also commonly increased in a pocket portion along the drain. The resulting IGFET is then typically a symmetric device.
FIG. 1 illustrates such a conventional long-channel symmetric n-channel IGFET 20 as described in U.S. Pat. No. 6,548,842 B1 (Bulucea et al.). IGFET 20 is created from a p-type monocrystalline silicon (“monosilicon”) semiconductor body. The upper surface of IGFET 20 is provided with recessed electrically insulating field-insulating region 22 that laterally surrounds active semiconductor island 24 having n-type source/drain (“S/D”) zones 26 and 28. Each S/D zone 26 or 28 consists of very heavily doped main portion 26M or 28M and more lightly doped, but still heavily doped, lateral extension 26E or 28E.
S/D zones 26 and 28 are separated from each other by channel zone 30 of p-type body material 32 consisting of lightly doped lower portion 34, heavily doped intermediate well portion 36, and upper portion 38. Although most of upper body-material portion 38 is moderately doped, portion 38 includes ion-implanted heavily doped halo pocket portions 40 and 42 that respectively extend along S/D zones 26 and 28. IGFET 20 further includes gate dielectric layer 44, overlying very heavily doped n-type polycrystalline silicon (“polysilicon”) gate electrode 46, electrically insulating gate sidewall spacers 48 and 50, and metal silicide layers 52, 54, and 56.
S/D zones 26 and 28 are largely mirror images of each other. Halo pockets 40 and 42 are also largely mirror images of each other so that channel zone 30 is symmetrically longitudinally graded with respect to channel dopant concentration. Due to the symmetry, either S/D zone 26 or 28 can act as source during IGFET operation while the other S/D zone 28 or 26 acts as drain. This is especially suitable for some digital situations where S/D zones 26 and 28 respectively function as source and drain during certain time periods and respectively as drain and source during other time periods.
The increased p-type dopant channel dopant concentration provided by each halo pocket 40 or 42 along S/D zone 26 or 28, specifically along lateral S/D extension 26E or 28E, causes surface punchthrough to be avoided. Upper body-material portion 38 is also provided with ion-implanted p-type anti-punchthrough (“APT”) semiconductor dopant that reaches a maximum concentration in the vicinity of the depth of S/D zones 26 and 28. This causes bulk punchthrough to be avoided.
Each sidewall spacer 48 or 50 is cross-sectionally shaped generally like a right triangle with a curved hypotenuse as viewed in the direction of the IGFET's width. Gate sidewall spacers of such cross-sectional shape are referred to here as curved triangular spacers. Other cross-sectional shapes are conventionally employed for gate side wall spacers. In some cases, the shapes of the gate sidewall spacers are modified significantly during IGFET fabrication so as to improve IGFET characteristics.
FIGS. 2a-2d (collectively “FIG. 2”) illustrate how the shape of a gate sidewall spacer changes as described in Augendre et al. (“Augendre”), “Thin L-shaped spacers for CMOS”, 33rd Eur. Solid-State Dev. Rsch. Conf., 16-18 Sep. 2003, pp. 219-222. The IGFETs in Augendre appear to be symmetric devices. FIG. 2 is centered on the spacer structure near an S/D zone and, for convenience, presents part of Augendre's n-channel implementation using the same reference symbols as in FIG. 1 for corresponding regions. At the stage of FIG. 2a, precursor 28EP to S/D extension 28E has been formed. Lower dielectric layer 58A of silicon oxide, intermediate dielectric layer 58B of silicon nitride, upper dielectric layer 58C of silicon oxide, and polysilicon layer 58D have been successively provided along the upper semiconductor surface and along gate electrode 46.
An anisotropic etch is performed to remove all of polysilicon layer 58D except for portions along the vertical parts of upper silicon oxide layer 58C. See FIG. 2b. Item 58DR indicates a remaining portion of polysilicon layer 58D. The portions of upper oxide layer 58C not covered by the remaining portions, e.g., portion 58DR, of polysilicon layer 58D are also removed. Curved triangular gate sidewall spacer 58T then consists of remaining polysilicon portion 58DR, remaining upper oxide portion 58CR, and the underlying portions of intermediate silicon nitride layer 58B and lower silicon oxide layer 58A. Using gate electrode 46 and curved triangular spacer 58T as a dopant-implantation shield, n-type main S/D semiconductor dopant is ion implanted to define main S/D portion 28M. S/D extension 28E is the segment of precursor S/D extension 28EP outside main S/D portion 28M.
Referring to FIG. 2c, the exposed parts of nitride layer 58B are removed. Item 58BR indicates a remaining portion of nitride layer 58B. Polysilicon spacer portion 58DR is removed. Upper oxide portion 58CR and the other remaining portions of upper oxide layer 58C are removed. In so doing, the exposed parts of lower oxide layer 58A are removed. Item 58AR indicates a remaining portion of lower oxide layer 58A. As a result, curved triangular spacer 58T is converted into L-shaped gate sidewall spacer 58L consisting of L-shaped lower oxide portion 58AR and overlying L-shaped nitride portion 58BR.
A layer of cobalt is deposited on the structure of FIG. 2c to begin a self-aligned silicidation process commonly referred to as “salicidation”. A titanium cap layer is deposited on the cobalt layer. The cobalt overlying gate electrode 46 and main S/D portion 28M is reacted with underlying silicon to form metal silicide layers 52 and 56. The cobalt overlying the L-shaped spacers, including spacer 58L, does not undergo reaction. The titanium cap layer is removed followed by removal of the unreacted cobalt, i.e., the cobalt overlying the L-shaped spacers. FIG. 2d depicts the resultant structure. Augendre reports that use of L-shaped spacers during salicidation leads to more uniform tungsten deposition, and enables IGFETs to be packed more closely together, compared to using curved triangular spacers during salicidation.
U.S. Pat. Nos. 6,664,156 B1, 6,815,355 B2, and 6,924,180 B2 describe other IGFET fabrication processes which utilized L-shaped gate sidewall spacers in fabricating symmetric IGFETs. In U.S. Pat. No. 6,924,180, a gate stack consisting of a gate electrode and an underlying gate dielectric layer is defined over a semiconductor body at the location for an n-channel IGFET. Using the gate electrode and thin silicon oxide layers along the gate electrode's lateral sides as an implantation shield, ion implantation is employed to form precursors to n-type S/D extensions akin to S/D extensions 26E and 28E of FIG. 1 and to form p-type precursors to shallow pocket portions akin to halo pocket portions 40 and 42 of FIG. 1. Curved triangular spacers configured similar to curved triangular spacer 58T of FIG. 2 are formed along the lateral sides of the gate electrode. Each spacer consists of an L-shaped dielectric portion and a curved triangular dielectric portion that fills the intervening space. Heavily doped n-type main S/D portions akin to main S/D portions 26M and 28M of FIG. 1 are defined by ion implantation using the gate electrode and the curved triangular spacers as an ion-implantation shield to complete the implantations for the S/D zones.
Similar to Augendre, the curved triangular portions of the gate sidewall spacers are removed at this point in the fabrication process of U.S. Pat. No. 6,924,180 to convert them into L-shaped spacers. Using the gate electrode and the L-shaped spacers as an ion-implantation shield, ion implantation is employed to define a pair of deep p-type pocket portions which extend respectively along the S/D zones up respectively to the shallow pocket portions. The structure is then annealed. U.S. Pat. No. 6,924,180 indicates that the deep pocket portions help alleviate punchthrough.
Various types of wells have been employed in integrated circuits (“ICs”), particularly ICs containing complementary IGFETs where wells must be used for either the n-channel or p-channel IGFETs depending on whether the lightly doped starting semiconductor material for the IGFET body material is of p-type or n-type conductivity. ICs containing complementary IGFETs commonly use both p-type and n-type wells in order to facilitate matching of n-channel and p-channel IGFET characteristics.
Early complementary-IGFET (“CIGFET”) fabrication processes, commonly termed “CMOS” fabrication, often created wells, referred to here as “diffused” wells, by first introducing main semiconductor well dopant shallowly into lightly doped semiconductor material prior to formation of a recessed field-insulating region typically consisting largely of thermally grown silicon oxide. Because the field-oxide growth was invariably performed at high temperature over a multi-hour period, the well dopant diffused deeply into the semiconductor material. As a result, the maximum concentration of the diffused well dopant occurred at, or very close to, the upper semiconductor surface. Also, the vertical profile of the diffused well dopant was relatively flat near the upper semiconductor surface.
In more recent CIGFET fabrication processes, ion implantation at relatively high implantation energies has been utilized to create wells subsequent to formation of the field oxide. Since the well dopant is not subjected to the long high-temperature operation used to form the field oxide, the maximum concentration of the well dopant occurs at a significant depth into the semiconductor material. Such a well is referred to as a “retrograde” well because the concentration of the well dopant decreases in moving from the subsurface location of the maximum well-dopant concentration to the upper semiconductor surface. Retrograde wells are typically shallower than diffused wells. The advantages and disadvantages of retrograde wells are discussed in (a) Brown et al., “Trends in Advanced Process Technology—Submicrometer CMOS Device Design and Process Requirements”, Procs. IEEE, December 1986, pp. 1678-1702, and (b) Thompson et al., “MOS Scaling: Transistor Challenges for the 21st Century”, Intel Technology J., Q398, 1998, pp. 1-19.
FIG. 3 illustrates symmetric n-channel IGFET 60 that employs a retrograde well as generally described in Rung et al. (“Rung”), “A Retrograde p-Well for Higher Density CMOS”, IEEE Trans Elec. Devs., October 1981, pp. 1115-1119. Regions in FIG. 3 corresponding to regions in FIG. 1 are, for simplicity, identified with the same reference symbols. With this in mind, IGFET 60 is created from lightly doped n-type substrate 62. Recessed field-insulating region 22 is formed along the upper semiconductor surface according to the local-oxidation-of-silicon process. P-type retrograde well 64 is subsequently formed by selectively implanting p-type semiconductor dopant into part of substrate 62. The remaining IGFET regions are then formed to produce IGFET 60 as shown in FIG. 3.
The p-type dopant concentration of retrograde well 64 is at moderate level, indicated by the symbol “p”, in the vicinity of the peak well dopant concentration. The well dopant concentration drops to a low level, indicated by the symbol “p−”, at the upper semiconductor surface. The dotted line in FIG. 3 indicates generally where the well dopant concentrations transitions from the p level to the p− level in moving from the p portion of well 64 to the upper semiconductor surface.
FIG. 4 indicates the general nature of the dopant profile along an imaginary vertical line through the longitudinal center of IGFET 60 in terms of net dopant concentration NN. Curve segments 62* and 64* respectively represent the net dopant concentrations of n-type substrate 62 and p-type retrograde well 64. Arrow 66 indicates the location of the maximum subsurface p-type dopant concentration in well 64. For comparison, curve segment 68* represents the vertical dopant profile of a typical deeper p-type diffused well.
A specific example of the dopant profile along an imaginary vertical line through the longitudinal center of retrograde well 64 as simulated by Rung is depicted in FIG. 5 in terms of net dopant concentration NN. Curve segment 26′ or 28′ indicates the individual n-type dopant concentration along an imaginary vertical line through S/D zone 26 or 28 of Rung's simulation of IGFET 60. As FIG. 5 indicates, the concentration of the p-type well dopant decreases by more than a factor of 10 in moving from location 66 of the maximum p-type dopant concentration in well 64 to the upper semiconductor surface. FIG. 5 also indicates that the depth of location 66 is approximately twice as deep as S/D zone 26 or 28 in IGFET 60.
A retrograde IGFET well, such as well 64, whose maximum well dopant concentration (i) is at least a factor of 10 greater than the well dopant concentration at the upper semiconductor surface and (ii) occurs relatively deep compared to, e.g., deeper than, the maximum depth of the S/D zones can be viewed as an “empty” well since there is a relatively small amount well dopant near the top of the well where the IGFET's channel forms. In contrast, a diffused well, i.e., a well in which semiconductor well dopant is introduced shallowly into lightly doped semiconductor material and then diffused deeply into the semiconductor material, is a “filled” well. The well for symmetric IGFET 20 in FIG. 1 can likewise be viewed as a filled well since the APT dopant “fills” the retrograde well that would otherwise occur if the main well dopant were the only well dopant.
A symmetric IGFET structure is generally not needed in situations where current flows in only one direction through an IGFET during device operation. As further discussed in U.S. Pat. No. 6,548,842, drain-side halo pocket portion 42 of symmetric IGFET 20 can be deleted to produce long n-channel IGFET 70 as shown in FIG. 6a. IGFET 70 is an asymmetric device because channel zone 30 is asymmetrically longitudinally dopant graded. S/D zones 26 and 28 in IGFET 70 normally respectively function as source and drain. FIG. 6b illustrates asymmetric short n-channel IGFET 72 corresponding to long-channel IGFET 70. In IGFET 72, source-side halo pocket 40 closely approaches drain 28. Asymmetric IGFETs 70 and 72 receive the same APT and well implants as symmetric IGFET 60.
U.S. Pat. Nos. 6,078,082 and 6,127,700 (both Bulucea) describe IGFETs having asymmetric channel zones but different vertical dopant concentration characteristics than those employed in the inventive IGFETs of U.S. Pat. No. 6,548,842. IGFETs having asymmetric channel zones are also examined in other prior art documents such as (a) Buti et al., “Asymmetrical Halo Source GOLD drain (HS-GOLD) Deep Sub-half Micron n-MOSFET Design for Reliability and Performance”, IEDM Tech. Dig., 3-6 December 1989, pp. 26.2.1-26.2.4, (b) Chai et al., “A Cost-Effective 0.25 μm Leff BiCMOS Technology Featuring Graded-Channel CMOS (GCMOS) and a Quasi-Self-Aligned (QSA) NPN for RF Wireless Applications”, Procs. 2000 Bipolar/BiCMOS Circs. and Tech. Meeting, 24-26 Sep. 2000, pp. 110-113, (c) Ma et al., “Graded-Channel MOSFET (GCMOSFET) for High Performance, Low Voltage DSP Applications”, IEEE Trans. VLSI Systs. Dig, December 1997, pp. 352-358, and (d) Su et al., “A High-Performance Scalable Submicron MOSFET for Mixed Analog/Digital Applications”, IEDM Tech. Dig., December 1991, pp. 367-370.
Choi et al. (“Choi”), “Design and analysis of a new self-aligned asymmetric structure for deep sub-micrometer MOSFET”, Solid-State Electronics, Vol. 45, 2001, pp. 1673-1678, describes an asymmetric n-channel IGFET configured similarly to IGFET 70 or 72 except that the source extension is more heavily doped than the drain extension. Choi's IGFET also lacks a well region corresponding to intermediate well portion 36. FIG. 7 illustrates Choi's IGFET 80 using the same reference symbols as used for IGFET 70 or 72 to identify corresponding regions. Although source extension 26E and drain extension 28E are both labeled “n+” in FIG. 7, the doping in source extension 26E of IGFET 80 is somewhat more than a factor of 10 greater than the doping in drain extension 28E. Choi indicates that the heavier source-extension doping should reduce the increased source-associated parasitic capacitance that otherwise results from the presence of halo pocket 40 along source 26.
FIGS. 8a-8d (collectively “FIG. 8”) represent steps in Choi's process for fabricating IGFET 80. Referring to FIG. 8a, precursor layers 44P and 46P respectively to gate dielectric layer 44 and polysilicon gate electrode 46 are successively formed along lightly doped p-type monosilicon wafer 34P that constitutes a precursor to body-material portion 34. A layer of pad oxide is deposited on precursor gate-electrode layer 46P and patterned to produce pad oxide layer 82. A layer of silicon nitride is deposited on top of the structure and partially removed to produce nitride region 84 that laterally abuts pad oxide 82 and leaves part of gate-electrode layer 46P exposed.
After removing the exposed part of gate-electrode layer 46P, arsenic and boron difluoride are ion implanted through the exposed part of dielectric layer 44P to define precursors 26EP and 40P respectively to n+ source extension 26E and p+ source-side halo pocket 40 as indicated in FIG. 8b. Nitride region 84 is converted into silicon nitride region 86 that laterally abuts pad oxide 82 and covers the previously exposed part of dielectric layer 44P. See FIG. 8c. After removing pad oxide 82, the exposed part of gate-electrode layer 46P is removed to leave the remainder of layer 46P in the shape of gate electrode 46 as shown in FIG. 8d. Another part of dielectric layer 44P is thereby exposed. Arsenic is ion implanted through the newly exposed part of dielectric layer 44P to define precursor 28EP to n+ drain extension 28E. In later steps (not shown), nitride 86 is removed, gate sidewall spacers 48 and 50 are formed, arsenic is ion implanted to define n++ main S/D portions 26M and 28M, and a rapid thermal anneal is performed to produce IGFET 80 as shown in FIG. 7.
Choi's decoupling of the source-extension and drain-extension implants and then forming source extension 26E at a considerably higher doping than drain extension 28E in order to alleviate the increased source-associated parasitic capacitance resulting from source-side halo pocket 40 is clearly advantageous. However, Choi's coupling of the formation of gate electrode 46 with the formation of source/drain extensions 26E and 28E in the process of FIG. 8 is laborious and could make it difficult to incorporate Choi's process into a larger semiconductor process that provides other types of IGFETs. It would be desirable to have a simpler technique for making such an asymmetric IGFET. In particular, it would be desirable to decouple the gate-electrode formation from the formation of differently doped source/drain extensions.
The conventional IGFETs dealt with above generally operate across a voltage range of several volts down to two volts or less. Some IGFET fabrication platforms furnish these IGFETs in “high-voltage” and “low-voltage” forms. The high-voltage IGFETs operate across several volts, e.g., 3-5 volts. The low-voltage IGFETs simply operate across a smaller voltage range than the high-voltage IGFETs in any particular semiconductor structure containing both types of IGFETs. The gate dielectric layer thickness is typically greater for the high-voltage IGFETs than for the low-voltage IGFETs so that the high-voltage IGFETs can withstand higher voltages. The high-voltage IGFETs normally have threshold voltages of greater magnitude than the low-voltage IGFETs.
Some IC applications require considerably higher operating voltage ranges, e.g., ranges up to 10 volts or more. While it might be possible to make relatively minor modifications in the IGFETs dealt with above so as to accommodate such extended operating voltage ranges, better performance is typically achieved by using IGFETs of significantly different configurations. Asymmetric IGFETs which employ the general IGFET configuration referred to as extended-drain (or drain-extended) MOS are particularly suitable for operating across voltage ranges of 10 volts or more. Extended-drain IGFETS, often referred to as laterally diffused MOS (“LDMOS”), are described in (a) Brisbin et al., “Hot-Carrier Reliability and Design of N-LDMOS Transistor Arrays”, 2001 IEEE Intg. Reliability Workshop Final Report, 15-18 Oct. 2001, pp. 44-48, (b) Wang et al., “Effect of Layout Orientation on the Performance and Reliability of High Voltage N-LDMOS in Standard Submicron Logic STI CMOS Process”, Procs. IEEE 43rd Ann. 2005 Int'l Reliability Phys. Symp., 17-21 Apr. 2005, pp. 654-655, (c) Tsui et al., “A Volatile Half-Micron Complementary BiCMOS Technology for Microprocessor-Based Smart Power Applications”, IEEE Trans. Elec. Devs., March 1995, pp. 564-570, and (d) Smayling et al., “A Modular Merged Technology Process including Submicron CMOS Logic, Nonvolatile Memories, Linear Functions, and Power Components”, Procs IEEE 1993 Custom Integrated Circuits Conf., 9-12 May 1993, pp. 24.5.1-24.5.4.
FIG. 9 illustrates n-channel extended-drain IGFET 90 of Brisbin et al., cited above, using the same reference symbols as used for IGFET 70 or 72 to identify corresponding regions. Main source portion 26M and more lightly doped source extension 26E of n-type source 26 in IGFET 90 are indicated here as being respectively at the “n+” and “n” doping levels rather than respectively at the “n++” and “n+” doping levels used in FIGS. 6a and 6b for IGFETs 70 and 72. Moderately doped p-type body region 92 formed by introducing p-type body semiconductor dopant into part of the semiconductor body extends along source 26 up to gate dielectric layer 44. Electrical contact to p body region 92 is made via heavily doped p-type body contact portion 94.
N-type drain 28 of IGFET 90 consists of lightly doped drift region 28D, moderately doped intermediate layer 28L, heavily doped surface-adjoining drain contact portion 28C, and heavily doped buried layer 28B. Although not stated in Brisbin, n− drift region 28D is presumably part of a lightly doped n-type epitaxial layer and is thus not formed by a separate doping operation. Drift region 28D extends up to gate dielectric layer 44 and is laterally separated from n+ drain contact portion 28C by part of recessed field insulation 22. Intermediate n layer 28L extends from contact portion 28C along that part of field insulation 22 down to drift region 28D. Polysilicon gate electrode 46 extends partway over that part of insulation 22 in IGFET 90.
N-channel IGFET 96 of Wang et al., cited above, is depicted in FIG. 10 again using the same reference symbols as used for IGFET 70 or 72 to identify corresponding regions. In IGFET 96, source 26 is simply a heavily doped n-type region and does not have a more lightly doped lateral extension. Body region 92 of IGFET 96 is a moderately doped p-type well electrically connected to the upper semiconductor surface via p+ body contact portion 94.
N-type drain 28 of IGFET 96 consists of moderately doped well 28W and heavily doped drain contact portion 28C. N well 28W extends up to gate dielectric layer 44. Recessed field insulation 22 laterally surrounds n+ drain contact portion 28C so that part of field insulation 22 laterally separates drain contact portion 28C from where n well 28W meets gate dielectric 44. As in IGFET 90, polysilicon gate electrode 46 extends partway over the part of insulation 22 in IGFET 96.
The term “mixed signal” refers to ICs containing both digital and analog circuitry blocks. The digital circuitry typically employs the most aggressively scaled n-channel and p-channel IGFETs for obtaining the maximum potential digital speed at given current leakage specifications. The analog circuitry utilizes IGFETs and/or bipolar transistors subjected to different performance requirements than the digital IGFETs. Requirements for the analog IGFETs commonly include high linear voltage gain, good small-signal and large-signal frequency response at high frequency, good parameter matching, low input noise, well controlled electrical parameters for active and passive components, and reduced parasitics, especially reduced parasitic capacitances. Although it would be economically attractive to utilize the same transistors for the analog and digital blocks, doing so would typically lead to weakened analog performance. Many requirements imposed on analog IGFET performance conflict with the results of digital scaling.
More particularly, the electrical parameters of analog IGFETs are subjected to more rigorous specifications than the IGFETs in digital blocks. In an analog IGFET used as an amplifier, the output resistance of the IGFET needs to be maximized in order to maximize its intrinsic gain. The output resistance is also important in setting the high-frequency performance of an analog IGFET. In contrast, the output resistance is considerably less importance in digital circuitry. Reduced values of output resistance in digital circuitry can be tolerated in exchange for higher current drive and consequent higher digital switching speed as long as the digital circuitry can distinguish its logic states, e.g., logical “0” and logical “1”.
The shapes of the electrical signals passing through analog transistors are critical to circuit performance and normally have to be maintained as free of harmonic distortions and noise as reasonably possible. Harmonic distortions are caused primarily by non-linearity of transistor gain and transistor capacitances. Hence, linearity demands on analog transistors are very high. The parasitic capacitances at pn junctions have inherent voltage non-linearities that need to be alleviated in analog blocks. Conversely, signal linearity is normally of secondary importance in digital circuitry.
The small-signal analog speed performance of IGFETs used in analog amplifiers is determined at the small-signal frequency limit and involves the small-signal gain and the parasitic capacitances along the pn junctions for the source and drain. The large-signal analog speed performance of analog amplifier IGFETS is similarly determined at the large-signal frequency limit and involves the non-linearities of the IGFET characteristics.
The digital speed of logic gates is defined in terms of the large-signal switching time of the transistor/load combination, thereby involving the drive current and output capacitance. Hence, analog speed performance is determined differently than digital speed performance. Optimizations for analog and digital speeds can be different, leading to different transistor parameter requirements.
Digital circuitry blocks predominantly use the smallest IGFETs that can be fabricated. Because the resultant dimensional spreads are inherently large, parameter matching in digital circuitry is often relatively poor. In contrast, good parameter matching is usually needed in analog circuitry to achieve the requisite performance. This typically requires that analog transistors be fabricated at greater dimensions than digital IGFETs subject to making analog IGFETS as short as possible in order to have source-to-drain propagation delay as low as possible.
In view of the preceding considerations, it is desirable to have a semiconductor fabrication platform that provides IGFETs with good analog characteristics. The analog IGFETs should have high intrinsic gain, high output resistance, high small-signal switching speed with reduced parasitic capacitances, especially reduced parasitic capacitances along the source-body and drain-body junctions. It is also desirable that the fabrication platform be capable of providing high-performance digital IGFETs.